module prime2(in,isprime);
  input [3:0] in;
  output isprime;
  //以下语句相当于
  //wire isprime; 
  //assign isprime = ...
  wire isprime = (in[0] & ~in[3]) |
                 (in[1] & ~in[2] & ~in[3]) |
		 (in[0] & ~in[1] & in[2]) |
		 (in[0] & in[1] & ~in[2]) ;
endmodule

